The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a partial silicon-on-insulator (SOI) substrate.
As semiconductor devices are becoming highly efficient, semiconductor integration technology using SOI wafer is drawing interest for replacing a single crystal silicon wafer with bulk silicon. The reason for drawing such interest is that a semiconductor device integrated on an SOI substrate has advantages over a typical semiconductor device integrated on a single crystal silicon substrate. The advantages include small junction capacitance resulting in a higher speed, low threshold voltage resulting in low voltage, and complete device isolation resulting in latch-up removal.
Meanwhile, a partial SOI process has been recently introduced. The partial SOI process refers to a process in which an insulation layer is formed locally in a stack structure including silicon/insulation/bulk silicon.
In FIG. 1 of a non-patent reference by Jong-man Park et al, entitled “A Novel Body Effect Reduction Technique to Recessed Channel Transistor Featuring Partially Insulating Layer Under Source and Drain: Application to Sub-50 nm DRAM Cell,” International Electron Devices Meeting (IEDM) 2007, IEEE International, pp. 903-906, a method for fabricating a partial SOI substrate is illustrated.
FIGS. 1A to 1F illustrate cross-sectional views of a method for fabricating a typical partial SOI substrate.
Referring to FIG. 1A, a silicon germanium (SiGe) layer 102 is formed over a first silicon layer 101, and a second silicon layer 103 is formed over the silicon germanium layer 102.
Referring to FIG. 1B, certain portions of the second silicon layer 103 and the silicon germanium layer 102 are etched for forming a partial SOI substrate. Reference numbers 102A and 103A represent a silicon germanium pattern 102A and a second silicon pattern 103A, respectively.
Referring to FIG. 1C, a third silicon layer 104 is formed over the substrate structure. The silicon germanium pattern 102A represents regions where a partial SOI is to be formed.
Referring to FIG. 1D, the third silicon layer 104, the second silicon pattern 103A, and the first silicon layer 101 are etched to form trenches 105. The silicon germanium pattern 102A is also etched when forming the trenches 105. Reference numbers 101A, 102B, 103B, and 104A represent a remaining first silicon layer 101A, a remaining silicon germanium pattern 102B, a remaining second silicon pattern 103B, and a remaining third silicon layer 104A, respectively.
Referring to FIG. 1E, the remaining silicon germanium pattern 102B (shown in FIG. 1D) exposed by the trenches 105 is removed. As a result, portions where the remaining silicon germanium pattern 102B used to be become spaces 106.
Referring to FIG. 1F, an insulation layer is formed over the substrate structure in a manner that the insulation layer fills the trenches 105 and the spaces 106 to form a device isolation region 107.
As described above, the method for fabricating a typical partial SOI substrate includes a formation process of the silicon germanium layer 102 between the first silicon layer 101 and the second silicon layer 103, and a selective removal process performed when forming the device isolation region 107, thereby forming a partial SOI in an active region. Using a partial SOI substrate allows maintaining a high threshold voltage and controlling extension of charge depletion.
However, the typical method generally requires performing an epitaxial growth process at least three times. The processes are shown in the typical method described above where the silicon germanium layer 102, the second silicon layer 103, and the third silicon layer 104 are formed. Therefore, the cost of the process increases due to the complexity and issues related to mass-production.
Also, when the second silicon layer 103 and the silicon germanium layer 102 are etched to form the second silicon pattern 103A and the silicon germanium pattern 102A in FIG. 1B, respectively, the silicon germanium pattern 102A is exposed, causing contamination of the chamber by germanium (Ge).
Furthermore, a high temperature may not be applied to the silicon germanium pattern 102A in a subsequent process because inner diffusion may occur at a high temperature. Thus, a thermal budget may be decreased.
For a metallic element such as germanium, diffusion may occur depending on chamber contamination and temperature.
Therefore, a high temperature may not be used when forming the third silicon layer 104. As a result, a long period of time may be needed to form the third silicon layer 104 and the quality of the layer may be deteriorated.